MCQ in Computer Fundamentals Part 3 | ECE Board Exam

This is the Multiple Choice Questions Part 3 of the Series in Computer Fundamentals as one of the Electronics Engineering topic. In Preparation for the ECE Board Exam make sure to expose yourself and familiarize in each and every questions compiled here taken from various sources including but not limited to past Board Exam Questions in Electronics Engineering field, Electronics Books, Journals and other Electronics References.

MCQ Topic Outline included in ECE Board Exam Syllabi

• MCQ in analog and Digital System
• MCQ in Binary Number System
• MCQ in Boolean Algebra
• MCQ in Mathematical Logic and Switching Networks
• MCQ in Basic digital Circuits (logic gates, flip-flops, multivibrators, etc)
• MCQ in Static and dynamic Memory Devices
• MCQ in Programming and Machine Languages
• MCQ in Information and Acquisition Processing
• MCQ in Analog / Digital Conversion
• MCQ in Computer Networking

Continue Practice Exam Test Questions Part 3 of the Series

⇐ MCQ in Computer Fundamentals Part 2 | ECE Board Exam

Choose the letter of the best answer in each questions.

101. Which of the following is NOT an advantage of state tables in sequential logic circuit design?

A. They are the systematic approach to a design problem

B. The number of variables is limited

C. They minimize the gating required

D. They result in synchronous circuit

102. A situation in a system where it can never leave or progress to another state.

A. Rest

B. Hang-up state

C. No change in state

D. Toggle

103. A diagram consisting of a set of circles, where each circle contains a number of states within it.

A. State table

B. Transition diagram

C. Karnaugh map

D. Bubble diagram

104. A counter that counts sequentially but does not step through all possible states, it returns to zero after a particular state.

A. Ripple counter

B. Decade counter

C. Truncated counter

D. Binary counter

105. A circuit that produces an output pulse for a fixed period of time in response to a trigger and then returns to its quiescent state.

A. Monostable circuit

B. Astable circuit

C. Bistable circuit

D. Discriminator

106. A small change made in resistance or capacitance to time a circuit precisely.

A. Trigger

B. Tweaking

C. Bounce

D. Squeaking

107. A square wave oscillator or clock generator

A. Astable circuit

B. Monostable circuit

C. Bistable circuit

D. Debounding circuit

108. A circuit designed to produce a clean output in response to a switch closure.

A. Monostable circuit

B. Filter circuit

C. Attenuator

D. Debouncing circuit

109. Duty cycle for repetitive waveform is defined as the

A. Ratio of the ON time to the total time

B. Sum of the ON time and the OFF time

C. Ratio of the OFF time to the ON time

D. Ratio of the total time to the ON time

110. The state of a flip-flop when Q = 0 and Q’ = 1

A. Reset

B. Set

C. Trigger state

D. Tristate

111. The state of a flip-flop when Q = 1 and Q’ = 0.

A. Reset

B. Latch

C. Set

D. Glitch

112. A state causing the flip-flop to change or reverse its state.

A. Reset

B. Set

C. Toggle

D. Non-toggle

113. How many flip-flops should be used to realize 32-count capacity?

A. 2

B. 4

C. 5

D. 6

114. The time difference which results when a clock may not arrive at all flip-flops at precisely the same time.

A. Glitch

B. Spike

C. Hold

D. Clock skew

115. A _______ condition that exists if a circuit output depends on which of two nearly simultaneous inputs arrive at a point in the circuit first.

A. glitch

B. skew

C. clear

D. race

116. A one-input JK flip-flop is the _______ flip-flop.

A. D

B. T

C. S-R

D. C

117. A JK flip-flop can be made to function like a T flip-flop by simply

A. connecting the J and K inputs together as one input

B. connecting J = 0 and K = 0

C. resetting all inputs of the JK

D. connecting earth ground the JK inputs

118. The one-input RS flip-flop is the _______ flip-flop.

A. T

B. D

C. R

D. Latch

119. Which of the following does not describe a flip-flop?

A. It is a one-bit memory device.

B. Its interval circuitry are usually symmetrical

C. It is a bistable device

D. It is equivalent to a one-shot circuit

120. In clock circuits, SWG means

A. square wave glitches

B. standard wire gauge

C. square wave generators

D. standard wave ground

121. An input signal that can activate or disable a gate.

A. Strobe

B. Glitch

C. Tristate

D. Wired-AND

122. A ring counter where the output is inverted and tied back to the input

A. Shift counter

B. Decade counter

C. BCD counter

D. Johnson counter

123. A circuit that goes through 2^n – 1 states in a random fashion.

A. Random generator

B. Pseudo-random sequence generator

C. Counting shift

D. Register

124. An input that disables multiplexers or demultiplexers when it is HIGH.

A. Strobe

B. Keyboard

C. Decoder

D. Binary input

125. Application of excessive current to a fuse in order to open it.

A. Shorting

B. Blowing

C. Breaking

D. Disconnecting

126. An outstanding advantage of LCDs from LEDs.

A. LCDs are organized as a 7-segment display for numerical read out

B. LCDs can be multiplexed

C. LCDs essentially act as a capacitor and consume almost no power

D. LCDs generates light

127. A computer language that enables Programmable Array Logic (PAL) users to generate a file that can be used to blow a PAL.

A. JEDEC

B. PALASM

C. TURBO C++

D. Visual C

128. A type of computer bus which is bidirectional.

A. Data bus

B. Address

C. Control bus

D. Calling bus

129. A table used by a PLD language such as PALASM, to calculate the expected outputs for a set of inputs.

A. Excitation table

B. State table

C. Simulation table

D. Truth table

130. A programmable block of logic within a gate array, that contains a flip-flop for storage and also allows the user to specify logic functions on its inputs.

A. Programmed block

B. PLD

C. Configurable logic block

D. Block diagram

131. This type of bus carries the memory address from the computer to the memory.

A. Data bus

B. Address bus

C. Control bus

D. Parallel bus

132. This bus carries lines that control the operation of the memory from the microprocessor to the memory.

A. Data bus

B. Address bus

C. Control bus

D. Bus lines

133. A register which holds the address of the word currently being accessed.

A. Hold register

B. Memory address register

C. Memory data register

D. Access register

134. A register which holds the data being written into or read out of the addressed memory location.

A. Hold register

B. Memory data register

C. Memory address register

D. Glitch register

135. A preproduction model of a system built for testing and debugging,

A. Wire list

B. Maybe (colloquial)

C. Prototype

D. Sample

136. Correcting the faults in a circuit or a system.

A. Buzz-out

B. Debugging

C. Trap

D. Fault corrector

137. There are _________ flip-flops for a 3-bit binary counter.

A. 2

B. 3

C. 4

D. 5

138. A sequential logic circuit where the storage elements commonly used are time-delay devices (usually gates).

A. Synchronous SLC

B. Asynchronous SLC

C. Counter

D. Register

139. A block added to the combinational logic circuit to form a sequential logic circuit is the

A. ROM

B. counter

C. clock

D. memory

140. The state of the flip-flop before the occurrence of a clock pulse is called as its

A. present state

B. next state

C. current input

D. present output

141. The state of the flip-flop after the occurrence of a clock pulse is called as its

A. current state

B. present state

C. next state

D. current input

142. It is said to be a universal gate because any digital system can be implemented with it.

A. NAND

B. AND

C. OR

D. Exclusive OR

143. A flip-flop which follows its input in the next state.

A. T

B. D

C. JK

D. RS

144. An n-bit binary parallel adder requires ________ in its least design.

A. n half adders

B. n half subtractor

C. n full adders

D. n half subtractor and n full adder

145. A magnitude comparator has 2^(2n) entries in the truth table where n =

A. number of inputs

B. number of comparator bits

C. number of outputs

D. number of inputs and outputs

146. An included input terminals in a magnitude comparator IC which is significant when both inputs compared are equal is called as its

A. setting

B. cascading inputs

C. input terminals

D. address

147. In designing a 16 x 1 multiplexer, how many selection lines are needed?

A. 2

B. 4

C. 16

D. 32

148. If F = xy + x’y’ Boolean expression is to be implemented using decoders and OR gates, the connection involves

A. 2 to 4 line decoder with 3 OR gates

B. 3 to 8 line decoder with 2 OR gates

C. 2 to 4 line decoder with 1 OR gate

D. 3 to 8 line decoder with 4 OR gates

149. How many AND gates and 4-bit binary adders are needed to implement a 2-bit to 3-bit binary multiplier?

A. 15 AND gates and three 4-bit binary adders

B. 2 AND gates and one 4-bit binary adder

C. 9 AND gates only

D. 6 AND gates and one 4-bit binary adder

150. From a 3-bit binary counter design using T flip-flops, determine the number of T flip-flops needed in its circuit implementation.

A. 1

B. 2

C. 3

D. 4

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Questions and Answers in Computer Fundamentals

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Complete List of MCQ in Electronics Engineering per topic